Assignment pin problem. Work and do not work?

Yes, thank you, Hardik.

#  TCL File Generated by Component Editor 8.0
#  Thu Oct 08 16:53:40 ICT 2009
#  DO NOT MODIFY
#  +-----------------------------------
#  | 
#  | tea_top "tea_top" v1.0
#  | null 2009.10.08.16:53:40
#  | 
#  | 
#  | D:/TEA/Fpga_TEA/TEA_3C25_0/tea_src/tea_top.v
#  | 
#  |    ./tea_top.v syn, sim
#  | 
#  +-----------------------------------
#  +-----------------------------------
#  | module tea_top
#  | 
set_module_property NAME tea_top
set_module_property VERSION 1.0
set_module_property GROUP ""
set_module_property DISPLAY_NAME tea_top
set_module_property TOP_LEVEL_HDL_FILE tea_top.v
set_module_property TOP_LEVEL_HDL_MODULE tea_top
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE false
set_module_property SIMULATION_MODEL_IN_VERILOG false
set_module_property SIMULATION_MODEL_IN_VHDL false
set_module_property SIMULATION_MODEL_HAS_TULIPS false
set_module_property SIMULATION_MODEL_IS_OBFUSCATED false
#  | 
#  +-----------------------------------
#  +-----------------------------------
#  | files
#  | 
add_file tea_top.v {SYNTHESIS SIMULATION}
#  | 
#  +-----------------------------------
#  +-----------------------------------
#  | parameters
#  | 
#  | 
#  +-----------------------------------
#  +-----------------------------------
#  | connection point avalon_slave_0
#  | 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 minimumUninterruptedRunLength 1
set_interface_property avalon_slave_0 bridgesToMaster ""
set_interface_property avalon_slave_0 isMemoryDevice false
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 addressSpan 1024
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 isNonVolatileStorage false
set_interface_property avalon_slave_0 addressAlignment DYNAMIC
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 printableDevice false
set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_sink
add_interface_port avalon_slave_0 rbus_slv_addr address Input 8
add_interface_port avalon_slave_0 rbus_slv_wr_data writedata Input 32
add_interface_port avalon_slave_0 rbus_slv_wr_strb write Input 1
add_interface_port avalon_slave_0 rbus_slv_rd_strb read Input 1
add_interface_port avalon_slave_0 rbus_slv_rd_data readdata Output 32
add_interface_port avalon_slave_0 rbus_slv_ack waitrequest_n Output 1
#  | 
#  +-----------------------------------
#  +-----------------------------------
#  | connection point clock_sink
#  | 
add_interface clock_sink clock end
set_interface_property clock_sink ptfSchematicName ""
add_interface_port clock_sink clk_sys clk Input 1
add_interface_port clock_sink rstsys_n reset_n Input 1
#  | 
#  +-----------------------------------
#  +-----------------------------------
#  | connection point conduit_end
#  | 
add_interface conduit_end conduit end
set_interface_property conduit_end ASSOCIATED_CLOCK clock_sink
add_interface_port conduit_end clk export Output 1
add_interface_port conduit_end cmd export Bidir 1
add_interface_port conduit_end data1 export Bidir 1
add_interface_port conduit_end data2 export Bidir 1
add_interface_port conduit_end data3 export Bidir 1
add_interface_port conduit_end data4 export Bidir 1
add_interface_port conduit_end rbus_slv_byte_en export Input 4
#  | 
#  +-----------------------------------