Altera_Forum
Honored Contributor
10 years agoAssign all zeroes to unsigned
Hi, I want to assign all zeroes to an unsigned signal. I've been using ( others => '0' ) for STD_LOGIC_VECTOR signals, but when i attempt to do the same for unsigned, i get an error:
Error (10500): VHDL syntax error at top.vhd(222) near text "others"; expecting "(", or an identifier ("others" is a reserved keyword), or unary operator Does this only work at the declaration of the signal? Can I use it within my process on reset for example? if not, is there another easy way to set a signal to all zeroes? ( i am trying to avoid typing it all out since I plan to change the size of these signals between subsequent runs. )