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cconger's avatar
cconger
Icon for New Contributor rankNew Contributor
7 years ago

Arria 10 GX PLL not producing correct phase shift

I have generated an Altera PLL using Quartus Prime Standard Edition 17.1. The PLL accepts a 50 MHz reference clock, and produces five output clocks: 50 MHz, 200 MHz, 200 MHz w/ 1250ps shift, 333 MH...
JonWay_altera's avatar
JonWay_altera
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi @CCong1​

Tested on QII v18.1std and Modelsim 10.6d.

It seemed to work fine.

I used your Qsys file, wrap it with a top file, recompiled and simulated it. I attached the folder.

To simulate, open up Modelsim. Go to <unzipped path>/simulation/modelsim

Run: do pllforum_run_msim_rtl_verilog.do

It should show as screenshot.

You will see outclk3 and outclk4 are shifted by 1250ps as expected.