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cconger
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7 years ago

Arria 10 GX PLL not producing correct phase shift

I have generated an Altera PLL using Quartus Prime Standard Edition 17.1. The PLL accepts a 50 MHz reference clock, and produces five output clocks: 50 MHz, 200 MHz, 200 MHz w/ 1250ps shift, 333 MH...
cconger's avatar
cconger
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7 years ago

Hi Nooraini! Thanks for the reply, unfortunately I have not resolved this issue yet. In simulation the phase shift of that one clock is still incorrect.

The silver lining is that my design is functioning properly in hardware, however I do not have the measurement equipment necessary for accurate measurement of two 200 MHz clocks to see if the synthesized design is producing the correct phase shift. It is possible it is correct in synthesis and this is a simulation-only problem, or it is possible that my design just happens to work regardless, and I can't be sure which.

If you could find an Intel resource to investigate this I would appreciate it. I attached the IP output in the original post, hopefully that can be used to help. Please let me know if I can provide any additional information.

My simulator is ModelSim - Intel FPGA Edition 10.5b