Forum Discussion
bitwise
Occasional Contributor
7 years agoThere are still templates for VHDL/Verilog/SystemVerilog built into QuartusII.
To use them, open a text editor window ("File/New" then select your HDL of choice) then either
(a) Right-click in the text window and select "Insert Template",
(b) Select "Edit / Insert Template" from the QuartusII menu, or
(c) Left-click on the scroll icon that is in the text editor toolbar.
These templates are for synthesis. If you want a test bench template then open your compiled project in QuartusII and select "Processing / Start / Start Test Bench Template Writer".
Hope that helps.
Craig