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RayHaynes1's avatar
RayHaynes1
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Approach to changing IO assignments in Qsys with script

I have a design where I need to change some pin assignments in Qsys between builds (an operational build and a backup build). Looking to fully automate the building of both designs. I have a working ...
Hdl
  • RayHaynes1's avatar
    RayHaynes1
    2 years ago

    Just to close this item out here is what I ended up doing, best way? probably not.

    I decided against using the revision feature because we use git version control using it would complicate things. If we didn't use git I would have definitely looked into using it.

    So what I ended up with is a bash script that copies each of the uniquely named .qsys files to the soc_system.qsys file and runs a makefile which builds the fpga. Only the uniquely named .qsys files are checked into git, the soc_system.qsys is not. If the I/O ever needs to be modified the working pair of uniquely named .qsys files will need to be updated manually but that is very rare in our system (we are in production support mode).

    Thanks for the different ideas.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

If you have multiple complete system designs (.qsys files), then you can use the revisions feature. Just set which .qsys to use for each revision. Revisions work with anything that can be changed in the .qsf file. That includes which files make up the project.

RayHaynes1's avatar
RayHaynes1
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

I guess my question would be how would I change the revision setting with a bash script? Currently running Quartus 16 and I trying to bring the design forward but many issues with the bootloader and other things. And I'm not currently running any TCL (haven't figured out how to mix bash scripting and TCL yet) so I think I'm ok with my current approach as kludgy as it is for now. Lots of other stuff to do.

But thanks again for responding. Just a small rant. I have been working with FPGA for decades now and they are the worse environment to do design in. I need to know bash, TCL, c, and others that escape me right now, all outside of the HDL which is the real meat of the project and I think my approach is cobbled together? The whole FPGA build environment is far worse. rant over.

Ray