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Bus width reduction is easy to avoid, I was just using it as an example, when blocks have many, many parameters, all adding/removing logic and changing port lists, it can be quite complicated. Again, it should be better. As for identifying "user generated" warnings, that's the problem, in that there is no way to tell what is user generated.
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I knew the bus reduction was just an example ... but I still don't see why any of the other 'complexities' warrant the uncontrolled proliferation of so many warnings. Like I said it is not just Altera, I have used IP of other parties as well and that produced a equally insane amount of warnings. So you ignore them and just hope your HW test or simulation (for the brave ones who simulate their top-level design) works.
If we can not better identify the 'user generated' warnings we have a strong case for the abolishment of those IP-generated warnings!
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It just came to mind that it is the 'encrypted IP' that generates most of the warning mess. Here I can understand that it is difficult to avoid warnings as you can not easily re-generate encrypted code if the user can choose between e.g. GMII, RGMII, of SGMII connections. Then again with a bit of effort this should be possible too.
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