annoying warning during synthesis.

I'm afraid you must keep on enduring those annoying warnings.

This is a known issue. It has been discussed in another thread some time ago and someone advanced a solution to avoid the warnings.

But, if I remember correctly, it was only a partial solution and it involved some extensive work to reorganize project file and paths, so I never tried myself.

If you are interested, try search the forum.

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Hi

During synthesis I get a lot of warning saying:

"Warning: Using design file some_name.vhd, which is not specified as a design file for the current project, but contains definitions for X design units and Y entities in project"

My project files are stored in libraries, and in the project settings I add the path to these libraries. the Quartus manage to find the files using these paths, but still generates these annoying warnings that clatter my reports.

What is the best way to define the path to each path? I hope I don't have to do it manually because I have a lot of them..

thanks in advance

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You have to add every 'user' .vhd (and .v, .tdf etc.) to the "Files" section under Settings. If you use .tdf files which include user .inc, then you must add the path of the .inc files to "Libraries" section.

You can suppress messages, including these warnings. It's a one time thing and then done. Right-click on them, I believe.

The reason its a warning is that the files are picked up implicitly(from what I've seen, very few tools let you do this), and though allowed, not the best practice. For example, I've found very few people that use this know its rules for finding a file and adding it. As long as only one file exists with the proper entity/module, it's fine since the worst thing that could happen is that it doesn't find the correct file, but if there are multiple files with the same entity/module, it can get a little dangerous, although to be honest, I've seldom heard of problems.

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Oh, and the reason it's a warning is for the user who wants to add everything explicitly, which is considered the safer practice. That way they don't see the warning at all, but when it does show up, they know to look at it. So it can be very helpful(i.e. I wouldn't want it to go away).

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I got used and even learned to appreciate to have to specifically add all user files to get rid of these warnings. Do you have a similarly correct way of getting rid of all the warnings generated by Altera IP? E.g a typical Qsys system (NIOS II, DDR2 HPC , SGDMA , TSE) generates almost a thousand 'Verilog' warnings, so whining about these 'Using design file xxx ..' warnings is almost academic (with excuses to Dave).

Ugh. Sorry, but not an easy one. In justification:

- It is difficult to write IP that has no warnings, but parameterized IP is significantly more difficult. (It's just too easy to let synthesis reduce a bus to the correct size of something like that).

- It is difficult to say a warning is all right under all conditions. We don't want to do a blanket suppression, as there may be cases where the user has hooked something up incorrectly, and the warnings in the IP are what would identify that. Although with too many warnings, it's probably too difficult to know what's real and what's not.

Anyway, it's difficult, but Altera should do a better job of it, no doubt about it. I know this is always on the radar, but not sure what/when will happen.

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Ugh. Sorry, but not an easy one. In justification:

- It is difficult to write IP that has no warnings, but parameterized IP is significantly more difficult. (It's just too easy to let synthesis reduce a bus to the correct size of something like that).

- It is difficult to say a warning is all right under all conditions. We don't want to do a blanket suppression, as there may be cases where the user has hooked something up incorrectly, and the warnings in the IP are what would identify that. Although with too many warnings, it's probably too difficult to know what's real and what's not.

Anyway, it's difficult, but Altera should do a better job of it, no doubt about it. I know this is always on the radar, but not sure what/when will happen.

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I'd say as an apology, rather? Relying on the synthesizer to reduce a bus to the correct size and not bother about the warning is pure laziness. Do not forget that the poor user has to search the messages for those warnings he's responsible for. And I always ponder whether those Altera warnings are benign or not, and whether it is me triggering them. Remember the old C-adagio: a warning is an error waiting to happen. And personally I don't think it is difficult to write warning free code (even parametrized) , it may be a bit more work though.

Blanket suppression of Altera (and others!) IP generated warnings may be not that good idea, but you don't expect me to wade through all 1000 warnings on every compile?

An idea: maybe Altera can create a 'user warning' class with associated colour for warnings triggered by 'user' code?

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An idea: maybe Altera can create a 'user warning' class with associated colour for warnings triggered by 'user' code?

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You mean something like "suppress by entity"?

can I add a file to the libraries so when I add the library to the project it will automatically add all the files? I believe .qip files do something similar for components generated by automatic tools.

as you mentioned I don't want to do a blanket suppression, but I'm not thrilled about including every single file either...

No, a separate warning class so we can recognize the warnings generated in our 'user' code from the ones generated by Altera and Third-Party IP.

.qip files are good idea, especially if you want to include a subtree of code. and .qip files can reference other .qip files.

They are text files so you can make your own quite easily. Again you add the .qip file to the "Files" section.