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Oh, and the reason it's a warning is for the user who wants to add everything explicitly, which is considered the safer practice. That way they don't see the warning at all, but when it does show up, they know to look at it. So it can be very helpful(i.e. I wouldn't want it to go away).
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I got used and even learned to appreciate to have to specifically add all user files to get rid of these warnings. Do you have a similarly correct way of getting rid of all the warnings generated by Altera IP? E.g a typical Qsys system (NIOS II, DDR2 HPC , SGDMA , TSE) generates almost a thousand 'Verilog' warnings, so whining about these 'Using design file xxx ..' warnings is almost academic (with excuses to Dave).
Honored Contributor
