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Altera_Forum's avatar
Altera_Forum
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13 years ago

Analysis & Synthesis, Fitter Warnings

I'm currently cleaning up my design, reducing and explaining as many of the remaining warnings as possible. However for the following warnings, I have no clue so far. Any explanation would be of great help...

analysis & synthesis:

Warning: Ignored DEDICATED_MULTIPLIER_CIRCUITRY parameter with setting "AUTO" for node

"PROC:\P:0:PRC|...|altmult_add:altmult_add_component|mult_add_tsb3:auto_generated|mac_out5"

Actually "AUTO" seems the setting with most freedom to me. What is it "ignored" and what's the impact? And the reason? From the fitter report, I learn that 4 DSP elements are used, as for similar (parallel) instances PROC:\P:1:PRC|... and PROC:\P:2:PRC|... which don't show the warning.

fitter:

There are a number of "ignored assignments" types, which I don't understand:

Name I.E. Ignored To Ignored Value Ignored Source

I/O Standard termination_blk0~r.._pad 1.8 V QSF Assignment

Global signal 1) sc_clk_dp[.] off Compiler or HDL Assignment

Sync. Ident. 2) reset_reg[.] FORCED_IF_ASYNCHRONOUS Compiler or HDL Assignment

1) M_phy_alt_mem_phy_seq_wrapper

2) alt_ddrx_reset_sync

What's happening here?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    For precision of my fitter "ignored assignments". The concerned assignments are set in the following generator made files:

    alt_ddrx_clock_and_reset.v

    (* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;

    M_phy_alt_mem_phy_seq_wrapper.v

    (* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;

    Although the fitter issues the "Ignored Assignment" warning, I have not seen the use of global nets for the wires in question. What does happen here?