Analysis & Synthesis, Fitter Warnings

For precision of my fitter "ignored assignments". The concerned assignments are set in the following generator made files:

alt_ddrx_clock_and_reset.v

(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;

M_phy_alt_mem_phy_seq_wrapper.v

(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;

Although the fitter issues the "Ignored Assignment" warning, I have not seen the use of global nets for the wires in question. What does happen here?