New Contributor
Super ContributorHi @Ranesh ,
parameter W_MCDMA_DATA = 256,
parameter W_MCDMA_EMPT = $clog2(W_MCDMA_DATA/8),
logic [(W_MCDMA_EMPT - 1):0] s_outbytecount;
Variable s_outbytecount is 5-bit variable. So it should range from 0 to 31 right.
If s_outbytecount is 0 means in line 151 if I change s_outbytecount to number 0, I'm getting the same error as before:
Error(13224): Verilog HDL or VHDL error at vector_capture.sv(151): index -8 is out of range [15:0] for 's_in_data'
If I change s_outbytecount to number 31, I'm also getting error:
Error(13224): Verilog HDL or VHDL error at vector_capture.sv(151): index 256 is out of range [15:0] for 's_in_data'
But there's no error if using logic s_outbytecount. Probably you can't use logic type in both for loop if statement and if block.
Btw, if this is a bug with Quartus, I should be able to compile the code with other synthesis tool. But I'm getting the same synthesis error with Vivado so I believe this is not a bug. Let me know if you manage to get it compiled with other synthesis tool.
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
New ContributorHi Sheng,
You cannot change s_outbytecount to 0 only in line 151, you have to change s_outbytecount in line 150 to 0 as well, because line 151 is constrained by line 150.. By changing value of s_outbytecount to 0 only in line 151, you are making logical error and regardless of compiler this would lead to an error.
Please do not play with s_outbytecount in line 151. You can notice that s_outbytecount is calculated in line 146 and 153.
If you want to change s_outbytecount to see line 151 behavior, you have to calculate (d - s_outbytecount) value in line 151.
W_MODULE_DATA = 16,
c_OUT_DATA_BYTE_CNT = 32,
c_IN_DATA_BYTE_CNT = 2 and
Line 148 to152:
148: for (int d = 0; d < c_OUT_DATA_BYTE_CNT; d++)
149: begin
150: if ((d >= s_outbytecount) && (d < (s_outbytecount + c_IN_DATA_BYTE_CNT)))
151: s_output_data[d] <= s_in_data[((W_MODULE_DATA - ((d - s_outbytecount) * 8))- 1) -: 8];
152: end
In line 148 d can take 0 to 31
In line 151 d is constrained to be from s_outbytecount to (s_outbytecount + c_IN_DATA_BYTE_CNT) - 1
Since W_MODULE_DATA = 16, ((d - s_outbytecount) * 8)) can take only 0 or 8.
when ((d - s_outbytecount) * 8)) = 0, ((W_MODULE_DATA - ((d - s_outbytecount) * 8))- 1) = 15
when ((d - s_outbytecount) * 8)) = 8, ((W_MODULE_DATA - ((d - s_outbytecount) * 8))- 1) = 7
So line 151 would not have any errors
In other words, ((d - s_outbytecount) * 8)) cannot be greater than 8 or less than 0.
Please concentrate only on line 142, 143 (these if statements are bound by for loop in line 140)
and 151(this if statement is bound by for loop in line 150).
Regards,
Ranesh
New ContributorHi Sheng,
There was a mistake in last line of my last reply:
The lie
"Please concentrate only on line 142, 143 (these if statements are bound by for loop in line 140)
and 151(this if statement is bound by for loop in line 150)."
is not correct. It should be
"Please concentrate only on line 142, 143 (these if statements are bound by for loop in line 140 and 145)
and 150 (this if statement is bound by for loop in line 148 and 152)."
Thank you.
Regards,
Ranesh
