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Ranesh's avatar
Ranesh
Icon for New Contributor rankNew Contributor
3 years ago

Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..

Hi, I have following error while Analysis & Synthesis using Qyartus 21.2 and 22.2: Error(13224): Verilog HDL or VHDL error at vector_capture.sv(143): index -8 is out of range [15:0] for 's_in_da...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi @Ranesh ,

The reason for the error is the value of parameter W_MODULE_DATA (256) in submodule vector_capture.sv being overridden by the value of parameter W_MODULE_DATA (16) in top-module vector_capture_synth_top.sv.

Thanks,

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

Ranesh's avatar
Ranesh
Icon for New Contributor rankNew Contributor
3 years ago

Hi Sheng,

Thank you for your answer.

What you are saying is correct, but that cannot be the reason for this error message.

From lines 26 and 27 of vector_capture_synth.sv

26: parameter W_MODULE_DATA = 16; // Supported data widths (8 bits to 256 bits) power of 2 (2^3 to 2^8)
27: parameter W_MODULE_DESC = 204; // less than or equal to 256

From lines 66 to 70 of vector_capture.sv are:

66: localparam c_DESCBYTEALIGNBITS = ((W_MODULE_DESC % > 0) ? (8 - (W_MODULE_DESC % 8)) : 3'b0;

c_DESCBYTEALIGNBITS = ((204 % > 0) ? (8 - (204 % 8)) : 3'b0

c_DESCBYTEALIGNBITS = 4
67: logic [((W_MODULE_DESC + c_DESCBYTEALIGNBITS) - 1):0] s_in_desc; // Configuration bus from feeder module

logic [((204 + 4) -1):0] s_in_des

logic [207:0] s_in_des
68: localparam c_IN_DESC_BYTE_CNT = ((W_MODULE_DESC + c_DESCBYTEALIGNBITS)/8);

c_IN_DESC_BYTE_CNT = ((204 + 4)/8)

c_IN_DESC_BYTE_CNT = ((208)/8)

c_IN_DESC_BYTE_CNT = 26
69: localparam c_IN_DATA_BYTE_CNT = (W_MODULE_DATA/8);

c_IN_DATA_BYTE_CNT = (16/8)

c_IN_DATA_BYTE_CNT = 2

70: localparam c_OUT_DATA_BYTE_CNT = (W_MCDMA_DATA/8);

c_OUT_DATA_BYTE_CNT = (256/8)

c_OUT_DATA_BYTE_CNT = 32

The lines 140 and 144 are in vector_capture.sv are:

140: for (int c = c_IN_DESC_BYTE_CNT; c < c_OUT_DATA_BYTE_CNT; c++)

(int c = 26; c < 32; c++)

c can take only 26, 27, 28, 29, 30 and 31
141: begin
142: if (c < (c_IN_DESC_BYTE_CNT + (c_IN_DATA_BYTE_CNT - s_in_empty)))

(c < (26 + (2 - s_in_empty)))

(c < (28 - s_in_empty))

if s_in_empty is 0

c can take only 26 and 27

if s_in_empty is 1

c can take only 26

143: s_output_data[c] <= s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8];

If c become 26, the line becomes

s_output_data[26] <= s_in_data[((16 - ((26 - 26) * 8)) - 1) -: 8]

s_output_data[26] <= s_in_data[((16 - ((0) * 8)) - 1) -: 8]

s_output_data[26] <= s_in_data[((16 - 0 - 1) -: 8]

s_output_data[26] <= s_in_data[15 -: 8]

s_output_data[26] <= s_in_data[15 : 8]

If c become 27, the line becomes

s_output_data[27] <= s_in_data[((16 - ((27 - 26) * 8)) - 1) -: 8]

s_output_data[27] <= s_in_data[((16 - ((1) * 8)) - 1) -: 8]

s_output_data[27] <= s_in_data[((16 - 8 - 1) -: 8]

s_output_data[27] <= s_in_data[7 -: 8]

s_output_data[27] <= s_in_data[7 : 0]

144: end

From the above calculations, c cannot take any values that drives the index of s_in_data to be -8.

Regards,

Ranesh