altmult_add

1. It is already pipelined.

2. Im not quite sure what you mean? do you mean 2 vectors with 3 elemenents in each:

sum(

a(0) * b(0)

a(1) * b(1)

a(2) * b(2)

);

?

In this case you need 3 multipliers and 2 adders.

I would suggest the altmult_add will probably work better than a custom made pipeline, if it suits your purpose. Why not simulate them and find out?

Thank you for your reply.

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1. It is already pipelined.

2. Im not quite sure what you mean? do you mean 2 vectors with 3 elemenents in each:

sum(

a(0) * b(0)

a(1) * b(1)

a(2) * b(2)

);

?

In this case you need 3 multipliers and 2 adders.

--- Quote End ---

i did mistake and yes you are right that i need 3 multipliers.

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I would suggest the altmult_add will probably work better than a custom made pipeline, if it suits your purpose.out?

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Thank you for suggestion.

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Why not simulate them and find

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I'm a beginner. Sometimes my simulation results may be different real works on DE2-115 board. Nevertheless i have trying to simulate.

Well, i have implemented my calculations in pipelined structures and i think that this type implementations need latencies of the pipelined blocks. i have searched to find whether altmult_add megafunction has a latency or output ready signal?

if i have to calculate the equation below how can i detect that the output of the altmult_add is ready for adder which will add the output of the altmult_add to 5?

sum(

a(0) * b(0)

a(1) * b(1)

a(2) * b(2)

) + 5;

Regards,

Bedri

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Thank you for your reply.

if i have to calculate the equation below how can i detect that the output of the altmult_add is ready for adder which will add the output of the altmult_add to 5?

sum(

a(0) * b(0)

a(1) * b(1)

a(2) * b(2)

) + 5;

Regards,

Bedri

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you need one mult (inputs a,b). accumulate results over 3 samples adding 5 as well. latency issues can be seen in simulation.

If there are differences between what you have in simulation and what you have in hardware, there is a problem.

The latency is always fixed, and depends on the settings you gave it. So you can always work out the latency based on the various clock source settings for the various registers: http://www.altera.co.uk/literature/ug/ug_lpm_alt_mfug.pdf