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Altera_Forum's avatar
Altera_Forum
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14 years ago

ALTMEMPHY DDR3 with QSys synthesis error

I realize that a similar error has already been discussed in the forum, but the solution that worked there does not seem to solve my issue.

When I attempt to synthesize a design containing a QSys system containing an ALTMEMPHY DDR3 I receive the following error:

Error: Input port DATAIN of DDIO_IN primitive "tenon_system:u0|tenon_system_altmemddr_0:altmemddr_0|tenon_system_altmemddr_0_controller_phy:tenon_system_altmemddr_0_controller_phy_inst|tenon_system_altmemddr_0_phy:tenon_system_altmemddr_0_phy_inst|tenon_system_altmemddr_0_phy_alt_mem_phy:tenon_system_altmemddr_0_phy_alt_mem_phy_inst|tenon_system_altmemddr_0_phy_alt_mem_phy_clk_reset:clk|ddio_mimic" must come from an I/O IBUF or DELAY_CHAIN primitive

Error: Output port "O" of PSEUDO_DIFF_OUT primitive "tenon_system:u0|tenon_system_altmemddr_0:altmemddr_0|tenon_system_altmemddr_0_controller_phy:tenon_system_altmemddr_0_controller_phy_inst|tenon_system_altmemddr_0_phy:tenon_system_altmemddr_0_phy_inst|tenon_system_altmemddr_0_phy_alt_mem_phy:tenon_system_altmemddr_0_phy_alt_mem_phy_inst|tenon_system_altmemddr_0_phy_alt_mem_phy_clk_reset:clk|DDR_CLK_OUT[0].mem_clk_pdiff" must drive only one OBUF primitive on the I port and cannot drive anything else

Note that this error does not occur when I migrate an ALTMEMPHY DDR3 design from SOPC Builder into QSys -- it only occurs when the QSys project is built from scratch.

It also does not occur in the 11.0sp1 PCIe to ALTMEMPHY reference design. I have repeatedly gone over that design looking for differences, but I can't seem to find any.

Note that when this error occurs, an "Info" message appears:

Info: WYSIWYG I/O primitives converted to equivalent logic

Info: WYSIWYG I/O primitive "tenon_system:u0|tenon_system_altmemddr_0:altmemddr_0|tenon_system_altmemddr_0_controller_phy:tenon_system_altmemddr_0_controller_phy_inst|tenon_system_altmemddr_0_phy:tenon_system_altmemddr_0_phy_inst|tenon_system_altmemddr_0_phy_alt_mem_phy:tenon_system_altmemddr_0_phy_alt_mem_phy_inst|tenon_system_altmemddr_0_phy_alt_mem_phy_clk_reset:clk|fb_clk" converted to equivalent logic

Info: WYSIWYG I/O primitive "tenon_system:u0|tenon_system_altmemddr_0:altmemddr_0|tenon_system_altmemddr_0_controller_phy:tenon_system_altmemddr_0_controller_phy_inst|tenon_system_altmemddr_0_phy:tenon_system_altmemddr_0_phy_inst|tenon_system_altmemddr_0_phy_alt_mem_phy:tenon_system_altmemddr_0_phy_alt_mem_phy_inst|tenon_system_altmemddr_0_phy_alt_mem_phy_clk_reset:clk|DDR_CLK_OUT[0].mem_clk_obuf" converted to equivalent logic

Warning: The following bidir pins have no drivers

Warning: Bidir "ddr3_clk_p" has no driver

Warning: Bidir "ddr3_clk_n" has no driver

On designs that compile, this message does not appear.

I am attaching a simplified project (11.0sp1) that demonstrates the issue.

Any help would be greatly appreciated.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    OK, I just figured this out.

    The top level design of the PCIe to ALTMEMPHY DDR3 reference design is in Verilog, so taking a stab in the dark, I converted the VHDL top level file of the previous project into Verilog -- and my synthesis issues went away.

    So returning to VHDL, I modified the component statement to remove all std_logic_vector(0 downto 0) to only std_logic. In other words -

    mem_mem_clk : inout std_logic_vector(0 downto 0) := (others => 'X');

    became

    mem_mem_clk : inout std_logic;

    When this process was complete, I attempted synthesis again, and had no errors.

    I'm not sure (1) why this matters to the synthesis tool or (2) why the Altera QSys tool generates VHDL examples that are not compatible with their synthesis tool, but at least this is a solution.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I had the same error when porting a stratix II design to Arria IIgx, changing SDRAM to DDR3. I tried creating a new project (SOPC builder and verilog only) using the golden_top file for the A2gx board, but that too had the problem.

    I eventually found that the golden_top file had the ddr3 clk outputs listed as "output" instead of "inout". That fixed the problem on both designs.