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Altera_Forum
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14 years ago

ALTMEMPHY DDR3 with QSys synthesis error

I realize that a similar error has already been discussed in the forum, but the solution that worked there does not seem to solve my issue. When I attempt to synthesize a design containing a QS...
Altera_Forum's avatar
Altera_Forum
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13 years ago

I had the same error when porting a stratix II design to Arria IIgx, changing SDRAM to DDR3. I tried creating a new project (SOPC builder and verilog only) using the golden_top file for the A2gx board, but that too had the problem.

I eventually found that the golden_top file had the ddr3 clk outputs listed as "output" instead of "inout". That fixed the problem on both designs.