ALTMEMPHY DDR3 with QSys synthesis error

OK, I just figured this out.

The top level design of the PCIe to ALTMEMPHY DDR3 reference design is in Verilog, so taking a stab in the dark, I converted the VHDL top level file of the previous project into Verilog -- and my synthesis issues went away.

So returning to VHDL, I modified the component statement to remove all std_logic_vector(0 downto 0) to only std_logic. In other words -

mem_mem_clk : inout std_logic_vector(0 downto 0) := (others => 'X');

became

mem_mem_clk : inout std_logic;

When this process was complete, I attempted synthesis again, and had no errors.

I'm not sure (1) why this matters to the synthesis tool or (2) why the Altera QSys tool generates VHDL examples that are not compatible with their synthesis tool, but at least this is a solution.