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zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
7 days ago
Solved

altera scfifo ip with power-up initial value

in the quartus 25.3 with agilex7,  I can  see the retiming restriction about scfifo power-up initial value in the retiming rpt.  from the altera user guide,  the scfifo sclr must be asserted by user ...
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  • RichardT_altera's avatar
    RichardT_altera
    4 days ago

    We recommend not to use initial power up conditions for Hyperflex Architecture. Resets should be used to put the chip into a known state. 
    If initial power-up conditions must be used, then we recommend that clocks be gated to prevent race conditions and functional errors by using the Reset Release IP. 

    If you verify that removing such initial conditions is functionally correct, you can specify the following .qsf assignment to remove those initial conditions:
    set_instance_assignment –name IGNORE_REGISTER_POWER_UP_INITIALIZATION ON –to <instance name>

    Please checkout the user guide below for further details:
    https://docs.altera.com/r/docs/683353/25.1.1/hyperflex-architecture-high-performance-design-handbook/initial-conditions-and-retiming

    Regards,
    Richard Tan

zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
4 days ago

Yeah，we never use the initial power up condition in the rtl code.  But we need to instantiate the scfifo IP, and the scfifo IP shows the retiming restriction about power-up initial value, not our user logic.

I have added the setting for scfifo ip.

set_instance_assignment –name IGNORE_REGISTER_POWER_UP_INITIALIZATION ON –to <instance name>

Will enabling this configuration together with synchronous reset affect the normal operation of the FIFO?