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Altera_Forum
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12 years ago

altera_attribute not working.

Hi All,

I want to cut the timing path between two nodes.I used altera_attribute in my verilog design file to cut the path between asynchronous nodes. From the timing report,its look like that this attribute is ignored and I am getting the set up violation. If I am applying same constraint in the sdc file,its working and I am not getting any set up time violation.

I have attached the design.

Thanks in advance,

Krupesh.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Change to:

    (* altera_attribute = {"-name SDC_STATEMENT \"set_false_path -from [get_registers *clk0_temp*] -to [get_registers *clk1_temp_f1*]\""} *)

    reg clk1_temp_f1;

    Note that it's almost like the command were in the .sdc, in that it isn't tied just to this hierarchy. I'm pretty sure it just runs the command and therefore you need to wildcard the hiearchy path to this level.

    If you want to keep .sdc constraints with HDL, another option is to create a .qip file that adds both the HDL and an .sdc for that HDL. This what Altera does for most of its IP. (In some cases they do embed constraints though...)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Thanks for the reply.

    I took the reference of Quartus Handbook 13.0 to embed timing constraint in Verilog.

    Example 17–126. Verilog-2001 and SystemVerilog Code: Applying altera_attribute with the -to

    Option

    reg reg2;

    (* altera_attribute = "-name CUT ON -to reg2" *) reg reg1;

    Anyway,given solution is working.

    I have one doubt that if I am going to encrypt this file,in that case also timequest recognize this constraint?

    Thanks,

    Krupesh