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Altera_Forum's avatar
Altera_Forum
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12 years ago

altera_attribute not working.

Hi All, I want to cut the timing path between two nodes.I used altera_attribute in my verilog design file to cut the path between asynchronous nodes. From the timing report,its look like that t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thanks for the reply.

I took the reference of Quartus Handbook 13.0 to embed timing constraint in Verilog.

Example 17–126. Verilog-2001 and SystemVerilog Code: Applying altera_attribute with the -to

Option

reg reg2;

(* altera_attribute = "-name CUT ON -to reg2" *) reg reg1;

Anyway,given solution is working.

I have one doubt that if I am going to encrypt this file,in that case also timequest recognize this constraint?

Thanks,

Krupesh