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Altera_Forum's avatar
Altera_Forum
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15 years ago

ALTDDIO_IN pipeline delay differs from documentation

I'm using MegaWizard on Quartus II 9.0 to generate a DDR input buffer, and the hardware being synthesized doesn't match the documentation. The documentation (http://www.altera.com/literature/ug/ug_altddio.pdf and http://www.altera.com/literature/hb/cyc/cyc_c51010.pdf) shows the same pipeline delay for both ddr_out_h and ddr_out_l. See the first attached image (Fig 10-1).

The logic actually produced is shown in the second attached image (RTL viewer screenshot). This delays ddr_out_l by one clock cycle relative to ddr_out_h. I've checked and invert clock input is not selected in MegaWizard. I can easily add a register to ddr_out_h to match the delay, but if Altera fixes this discrepancy, it could break the design. Is the documentation correct, or the implementation? Has this bug been fixed in a later version of Quartus? Figure 10–4 in http://www.altera.com/literature/hb/cyc/cyc_c51010.pdf also doesn't match the logic in Figure 10-1, data_in_h and data_in_l are swapped.

Thanks,

David

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The altddio user guide shows a circuit corresponding to the second (RTL) schematic in all versions I'm aware of (Figure 1-1 in V4.1 - V10.0). The Cyclone (I) Handbook circuit is actually different. Beginning with Cyclone II, the documentations seems to be consistent in this regard.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Is this also relevant to Cyclone IV devices? Other than this document I can't seem to find any specific Cyclone documentation that shows this, and Figure 3-1 seems to be specific to Apex II and Stratix series. If Figure 3-1 is correct, is the Cyclone handbook actually wrong, or not relevant to Cyclone II and above?

    I'm also somewhat confused by the invert_input_clocks parameter of the ALTDDIO_IN megafunction. Does this simply invert the input clock right at the front end and therefore the dataout_h and dataout_l outputs then become synchronous to the falling edge?

    Edit: More specifically, does dataout_h and dataout_l relate to the actual input clock edge rather than the inverted clock edge?

    It would be really useful to have a full diagram similar to Figure 3-1 for Cyclone devices showing this.

    Thanks,

    Mark.