ALTDDIO_IN pipeline delay differs from documentation

Is this also relevant to Cyclone IV devices? Other than this document I can't seem to find any specific Cyclone documentation that shows this, and Figure 3-1 seems to be specific to Apex II and Stratix series. If Figure 3-1 is correct, is the Cyclone handbook actually wrong, or not relevant to Cyclone II and above?

I'm also somewhat confused by the invert_input_clocks parameter of the ALTDDIO_IN megafunction. Does this simply invert the input clock right at the front end and therefore the dataout_h and dataout_l outputs then become synchronous to the falling edge?

Edit: More specifically, does dataout_h and dataout_l relate to the actual input clock edge rather than the inverted clock edge?

It would be really useful to have a full diagram similar to Figure 3-1 for Cyclone devices showing this.

Thanks,

Mark.