ALTASMI_PARALLEL Timequest Constraints

I have no idea how to get the name of the pin; the cycloneii_asmiblock component is defined in cycloneii.vhd (in quartus\eda\synthesis directory).

component cycloneii_asmiblock
    generic (
        lpm_type    :    string := "cycloneii_asmiblock"
    );
    port(
        data0out    :    out std_logic;
        dclkin    :    in std_logic;
        oe    :    in std_logic := '1';
        scein    :    in std_logic;
        sdoin    :    in std_logic
    );
end component;

This is fed from the altasmi_parallel megafunction and the ports are 'magically' (as far as I can tell) mapped to the active serial configuration device pins on the FPGA.

Using DCLK or dclk in TimeQuest does not work. Using Report Path... in TimeQuest from: * to: *DCLK returns the cycloneii_asmiblock2~ALTERA_DCLK as being at location PIN_12, which is the active serial DCLK pin and the last item in the list.

Any ideas anyone? I realise that this interface will probably work whether it is constrained or not, as it runs at less than 20MHz.

More generally it would be good if Altera put some actual examples for SPI-like peripherals and 'asynchronous' interfaces such as SRAMs that need to be constrained. Rysc's user guide is good, but has typos and does not look like it is going to be updated anytime soon to fix these or add content to the empty chapters.

Even better would be if the Quartus II Megawizard also produced a template SDC file for the IO of the ALTASMI_PARALLEL megafunction to the configuration device.