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Altera_Forum
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11 years ago

ALTASMI_PARALLEL Timequest Constraints

I'm using the ALTASMI_PARALLEL megafunction in a Cyclone III design and would like to know if anyone has SDC constraints for the DCLK, SDO, SCE outputs and DATA0 input. I've had a go myself, but bein...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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I'm not sure what you mean by 'add it as separate clk statement in sdc'. The derive_generated_clocks command produces the PLL clock and then I used a create_generated_clock for the DCLK pin. I was basing this on user dwh's 'TimeQuest Quad-SPI Flash Constraints Analysis' report.

Edit: That should be 'derive_pll_clocks command'

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where is your statement for dclk pin as a generated clk

The one above does not seem to refer to the dclk pin.