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Altera_Forum
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11 years ago

ALTASMI_PARALLEL Timequest Constraints

I'm using the ALTASMI_PARALLEL megafunction in a Cyclone III design and would like to know if anyone has SDC constraints for the DCLK, SDO, SCE outputs and DATA0 input. I've had a go myself, but bein...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The DCLK is sourced by PLL but is viewed as different timing node from its source since it is at pin level. So add it as separate clk statement in sdc.