ALTASMI_PARALLEL Timequest Constraints

After several days of trying different constraints, reading the TimeQuest User Guide and several other documents I'm still unable to figure out why TimeQuest keeps reporting that DCLK in unconstrained. When synthesizing the design the following warning is produced:

Warning: PLL "pll:pll0|altpll:altpll_component|pll_altpll:auto_generated|pll1" output port clk feeds output pin "flash_ctrl:flash_ctrl0|flash_if:flash_if0|flash_if_altasmi_parallel_f182:flash_if_altasmi_parallel_f182_component|cycloneii_asmiblock2~ALTERA_DCLK_OBUF" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

Running Report Unconstrained Paths in TimeQuest returns:

[from] pll0|altpll_component|auto_generated|pll1|clk[1]

[to] flash_ctrl:flash_ctrl0|flash_if:flash_if0|flash_if_altasmi_parallel_f182:flash_if_altasmi_parallel_f182_component|cycloneii_asmiblock2~ALTERA_DCLK

[from clocks] clk

is unconstrained in the Unconstrained Output Port Paths under both Setup and Hold Analysis.

Under Unconstrained Output Ports under both Setup and Hold Analysis:

[Output Port] flash_ctrl:flash_ctrl0|flash_if:flash_if0|flash_if_altasmi_parallel_f182:flash_if_altasmi_parallel_f182_component|cycloneii_asmiblock2~ALTERA_DCLK

[Comment] No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment.

Looking at the technology map viewer, this signal comes from the pll output, through an IO_BUF and to the pin.

Is this a bug in TimeQuest? Why would a generated clock need an output delay constraint? Should I just set it as a false path?