Forum Discussion
New ContributorAll code not being run every time
It's hard to tell without zooming in, but it looks like enc and enc_prev are going low simultaneously, so they wouldn't trigger the if statement at all. You might be seeing glitches because enc is not registered. It looks like a truly asynchronous input, so there's no guarantees with that if statement. I'd register enc and then do the if check.
If you do, you might also think about doing negedge enc in the sensitivity list.
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New ContributorThanks for the reply.
The enc and enc_prev are not quite simultaneous, since enc_prev is enc clocked at the next clock edge.
I have zoomed in to show it more clearly.
What is truly confusing me is if block has 4 lines.
- enc_pulse is taken high.
- count is incremented.
- enc_prev_time becomes enc_time.
- enc_time becomes now.
As you can see from the diagram (1) is being run, but (2-4) are not. How can this be?
n.b. I am currently using blocking assignments. I originally used non-blocking, but changed during my investigation. It made no difference.
if (enc == 0 && enc_prev == 1) begin // trigger on encoder falling edge enc_pulse = 1; count = count + 16'd1; enc_prev_time = enc_time; enc_time = now; end
I'm relatively new to verilog. What do you mean exactly by "registering enc"?
New ContributorI've worked out what you mean by "registering" by giving it more thought.
The code below does what I think you suggested. The 'missing_enc' line is my error detector that I trigger from in Signal Tap. This never triggers, so I think this is fixed. The alternative is that I have broken my error detector.
module encoder ( input clk, input enc, input [31:0] now, output reg [15:0] count, output enc_pulse, output missed_enc ); reg enc_reg; reg enc_prev; reg [31:0] enc_time; reg [31:0] enc_prev_time; assign enc_pulse = enc_prev & !enc_reg; assign missed_enc = (enc_time - enc_prev_time) > 64; // No initial block. First rev will always be invalid anyway. // System has no interest until up to speed. always @ (posedge clk) begin enc_prev <= enc_reg; enc_reg <= enc; end always @ (negedge enc_reg) begin count <= count + 16'd1; enc_prev_time <= enc_time; enc_time <= now; end endmodule
sstrellSuper Contributor
Yes, this is what I was talking about. Glad it's working correctly now.
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