Forum Discussion
Annu
New Contributor
New ContributorAHDL Simulation
How do we simulate an AHDL file in Text format using VHDL testbench using Quartus ii tool
KennyT_altera
Super Contributor
Super Contributorsorry for the late reply, what you can do is convert the file to the HDL files.
In Quartus prime std, click file -> create update -> create HDL file from current files.
Please take note that AHDL is already deprecated from the support.
