agilex7 retiming restriction

As indicated in the message, this retiming restriction occurs when the retimer has determined that a register has dangling connections, either its data input or output is unconnected or was optimized away.
1. Try to add pipeline regsiter between the Hyperpipe and SCFIFO.
Since the critical path is the physical distance between x_quartus_hyperpipe_rst_clk_fb_pipe and x_blk_fb|x_tdb|x_stream_buff_pkt_fifo, add explicit pipeline registers in your RTL at the boundary between these two modules.

2. Try to run Fast Forward Compile to get the tool specific recommendation. 
https://www.youtube.com/watch?v=2Sym26y3v7Y

Perhaps sharing a simplified design .QAR will help for further debugging. 

Regards,
Richard Tan