The warning is caused by the inferred RAM instance name changing between compilations. Although the RTL is unchanged, Quartus may rename internal inferred RAM nodes such as data_rtl_0 to data_rtl_1, so the back-annotated .tcl from the previous compile no longer matches the new design database.
This causes:
- Warning (15706) because the old node path no longer exists
- Warning (171007) because Quartus relaxes the exact low-level RAM cell assignment to a broader legal EAB location
Recommended action:
- regenerate the back-annotated assignments from the exact compile you want to preserve
- remove db/ and incremental_db/ before recompiling
- avoid constraining the deepest auto-generated inferred RAM node names
- if stable RAM placement is required, use explicit RAM/IP instantiation or a more stable hierarchy for assignment targeting
So the main issue is not RTL change, but name instability of inferred RAM implementation nodes across compilations.
Keep all compile conditions identical
- Quartus version
- seed
- synthesis settings
- fitter settings
- revision/database state
You may also attached your design.qar files for us to investigate.