Agilex 7 HPS how to read from port B of 2-port RAM

Hi Tiwari,

Thanks for coming back.

I have changed to use on-Chip Memory II (RAM or ROM) Intel FPGA IP. Can you help me to check its connection to the HPS' h2f_axi_master?

The pins on the on-chip memory's sides are

address2

read2

readdata2

byteenable2

write2

writedata2

address2, readdata2 and writedata2 can be connected to h2f_ARADDR, h2f_RDATA and h2f_WDATA respectively.

But I really don't know read2, write2, byteenable2 are connected to which pin of h2f_axi_master.

Please help.

Regards

Hi sstrell,

Thanks for coming back to me.

I did not connect individual signals.

Below shows my connection between my HPS' h2f_axi_master and on-chip memory II's s2. There is no problem with it.

The problem comes when you write the code.

If you open up the on-chip memory II, you will see these signals,

When you do the coding and if you want to, say read, you need to provide read2 signal with a high signal and also you byteenable2 signanls with high (depending which byte you want to read) before you can, actually, read.

read2 <= '1';

byteenable <= "1111"; -- assuming I wan to read all the 4 bytes

address2 <= "00 0000 0000 0000 1111"; -- assuming I want to read address 0x000F

readbuff <= readdata2; -- assuming readbuff is declared as signal readbuff : std_logic_vector (31 downto 0)

As you can see here, byteenable and read2 needs to be controlled by some pins at HPS's side.

So, which pins of HPS are controlling these byteenable and read2?

Regards