Agilex 7 HPS how to read from port B of 2-port RAM

You're either inferring or adding a standard RAM IP through Quartus. If you use the "On-Chip Memory II (RAM or ROM) Intel FPGA IP", it has options for an Avalon or, better yet, AXI4, interface to connect to the h2f interface.

https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/on-chip-memory-ii-ram-or-rom-intel-fpga-ip.html