GMcCa2
New Contributor
1 year agoAgilex 7 Compile Internal Error
I am getting an internal error during fitter in Quartus 24.1:
Sub-system: PHYCLK, File: /quartus/periph/phyclk/phyclk_gen7.cpp, Line: 1590.
I've attached the full error message, as well as an archive of a simplified project that creates the error.
The error seems to be related to having multiple instances of the LVDS SERDES IP. The design has 4 instances of the IP block created in the design through a generate for loop. If I modify the loop to be 0..0 instead of 0..3 then compilation completes with no errors.
Hi,
Check this kdb link https://www.intel.com/content/www/us/en/support/programmable/articles/000099084.html for 24.1 patch. This internal error had been fixed in 24.2 and onwards.
Thanks,
Regards,
Sheng