Agilex™ 7 R-Tile Compute Express Link* (CXL*) FPGA

Hi,

Before addressing your question, I would like to clarify a few things:

1. Are you using the Rtile FPGA DEV KIT and the CXL example design? If so, could you specify the model and Quartus version you are using?
2. Since CXL is based on PCIe 5.0, have we successfully run the PCIe 5.0 example design on the same card and correctly identified the device?
3. Additionally, have you checked whether your system supports the CXL protocol?

Best regards,
WZ