After synthesis, I can't see the state diagrams in state machine viewer

Hi,

problem with above posted code is that signal STATE is a combinational latch, not a clocked register.

Need to add clock edge sensitive condidtion, e.g.

    PROCESS(clk,OSPI_NCS)         
    BEGIN
	if rising_edge(clk) then 
        CASE STATE IS
            WHEN IDLE =>
                IF (OSPI_NCS = '0') THEN 
                    STATE <= DATA_PREPARE;
                ELSE
                    STATE <= IDLE;
                END IF;
            WHEN DATA_PREPARE =>
                OSPI_IO_TEMP <= SEND_DATA;
                DRDY <= '1';                                     --- data_ready ---
                STATE <= DATA_TRANSMIT;
            WHEN DATA_TRANSMIT =>
                IF(DRDY = '1' AND BYTE_COUNTER = 1) THEN
                     STATE <= IDLE;
                ELSE 
                     STATE <= DATA_TRANSMIT;
                END IF;
            WHEN OTHERS =>
                STATE <= IDLE;
        END CASE;
	end if;
    END PROCESS;