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Altera_Forum's avatar
Altera_Forum
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9 years ago

After change the hdl code,should I disable signaltap before recompile?

I have read article about using signaltap ii when design does not run correctly. It said I should set the top partition to Post-Fit. Then SignalTap is put into its own partition and therefore won't affect Top. Then I need to tap post-fit nodes though.

Now what I want to know is,after all operation above,if I change the hdl code to correct the problem,should I firstly disable signaltap and then compile the project?Because I think the design changed so that the post-fit results won't be preserved and re-place and re-route will be affect by signaltap.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Adding signaltap should not affect the design, other than possibly causing timing failures because it now struggles to fit from a large design. But it should not affect the design from an HDL point of view.

    What problems are you having?
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    I find it useful to place SignalTap in a LogicLock region where possible. While it is possible this will cause timing errors on the paths that SignalTap is adding, it allows you to move it all to a specific place in the FPGA which may be less used by your design and so it will cause fewer problems.

    If you are using it in a design which is very dense, then yes, it can cause problems - both in terms of timing as Tricky mentions, and also in terms of fitting - you may find your design fails to fit if there aren't enough resources for both it and SignalTap. This is especially true if you have a lot of taps or a large depth as the memory usage of block RAM can be quite large.

    I have on some designs had to disable ST and then compile any changes in post-fit mode, then re-enable ST and recompile. This was the only way to get the design to compile and meet timing. In other cases LogicLock regions helped pull all the ST nodes away from the densest parts of the design and so not cause timing issues. Finally in other cases, recompiling without disabling ST and not using post-fit didn't cause any issues - yes it moves the design around a bit, but on smaller designs it doesn't matter.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Thanks for reply,actually I don't encounter specific problem,it's just my thinking about influence of signaltap on place & route.What I know is that if the hdl code don't change and the 'top' partition is set as 'post-fit',signaltap will not affect the place & route because compiler won't re-place and re-route.But if the hdl code is changed,then the design will be re-synthesis,map,place and route based on incremental compilation theory.Will signaltap affect the compilation such as place and route ?though the 'top' partition is still post-fit.In other words,if I disable signaltap and recompilation the changed design,is the compilation results(place and route ,etc) same with that if I enable signaltap?

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Thanks for your help,what you said is what I want to know.I'll try to use logic-lock to solve the problem.