After change the hdl code,should I disable signaltap before recompile?

I find it useful to place SignalTap in a LogicLock region where possible. While it is possible this will cause timing errors on the paths that SignalTap is adding, it allows you to move it all to a specific place in the FPGA which may be less used by your design and so it will cause fewer problems.

If you are using it in a design which is very dense, then yes, it can cause problems - both in terms of timing as Tricky mentions, and also in terms of fitting - you may find your design fails to fit if there aren't enough resources for both it and SignalTap. This is especially true if you have a lot of taps or a large depth as the memory usage of block RAM can be quite large.

I have on some designs had to disable ST and then compile any changes in post-fit mode, then re-enable ST and recompile. This was the only way to get the design to compile and meet timing. In other cases LogicLock regions helped pull all the ST nodes away from the densest parts of the design and so not cause timing issues. Finally in other cases, recompiling without disabling ST and not using post-fit didn't cause any issues - yes it moves the design around a bit, but on smaller designs it doesn't matter.