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Altera_Forum
Honored Contributor
9 years agoThanks for reply,actually I don't encounter specific problem,it's just my thinking about influence of signaltap on place & route.What I know is that if the hdl code don't change and the 'top' partition is set as 'post-fit',signaltap will not affect the place & route because compiler won't re-place and re-route.But if the hdl code is changed,then the design will be re-synthesis,map,place and route based on incremental compilation theory.Will signaltap affect the compilation such as place and route ?though the 'top' partition is still post-fit.In other words,if I disable signaltap and recompilation the changed design,is the compilation results(place and route ,etc) same with that if I enable signaltap?