Add vhdl records as pin-assignments

Is it possible to create a design which his input/output ports are VHDL records and to make synthesizable and programmable?

Let's say I have a package I wrote and in it I define a record type:

package lib is
    type bla is record
        x:std_logic;
        y:std_logic_vector(3 downto 0);
    end record;
end package;

and I have the following design file:

use work.lib.all;
entity hello is
    port(
        world:in bla;
        output:out std_logic
    );
end entity;

From what I know, what I wrote is synthesizable but If I try to create a symbol file I get an error that it's not possible in the current version of Quartus or something like that..

therefor I have 2 questions:

1. Is it possible to create a symbol file (to put in a block-diagram-file) from such a design file like in my example?

2. Is it possible to create a project with pure VHDL and without *.BDF files and tell Quartus to that the pin-assignments for the record are something like that:

world.x

is assigned to pin_* (whatever) and

world.y

is assigned to a pin_* etc...