Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi BadOmen,
I have a question regarding the Avalon FIFO Memory. I have the input setup as MM, and the output as ST, with packets enabled. Now my question is, are the SOPs and EOPs are generated at for each beat? Say I have the settings as 8 bits per symbol and 4 symbols per beat. Will the SOP be generated on the 1st symbol, and the EOP is generated on the 4th symbol? I was under the impression, I can trigger an SOP and an EOP when I want, i.e. set the SOP bit, send many bytes of data ( definitely more than 4 symbols), set the EOP flag, and send the last byte of data. I could not find a timing diagram in the manual to check how the signalling works. https://www.altera.com/en_us/pdfs/literature/hb/nios2/qts_qii55002.pdf According to the manual, to set SOP, we have to write to the SOP offset at address 0x1, and then push the data at 0x0. Similarly for EOP, we first write offset 0x1 and then push the data at 0x0. On testing the core in my system, I never seem to be able to trigger on an EOP. The SOP is triggered, but it doesn't have a valid. I am still checking it via signaltap. In the meantime, any more information would be useful in checking if I connected the component wrongly in QSYS. Thank you, Divya