A/D converter-FPGA-USB

--- Quote Start ---

can anybody provide some basic idea to get digital data from A/D converter(HSMC) into cyclone IVE fpga and pass it into computer via USB port.

--- Quote End ---

Not really, your questions are too vague.

1) What ADC? How many bits and at what speed does it operate?

2) Which version of USB - 1.0 (12Mbps), 2.0 (480Mbps), or 3.0 (5Gbps)?

3) Do you have a specific board in mind? Since you mention HSMC, its likely you already have a board.

Provide this information and you'll get more help.

Cheers,

Dave

--- Quote Start ---

Not really, your questions are too vague.

1) What ADC? How many bits and at what speed does it operate?

--- Quote End ---

-->Highspeed AD/DA Card made by terasic for HSMC: 14-bit resolution and data rate up to 65 MSPS.

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=73&no=278&partno=1

and I want to use it as Analog to digital converter.

Although there are data pin configuration given in its user manual I am not sure about control pins how to map.

--- Quote Start ---

2) Which version of USB - 1.0 (12Mbps), 2.0 (480Mbps), or 3.0 (5Gbps)?

--- Quote End ---

-->In the user manual of DE2-115, it is given that: USB rev. 2.0 data transfer at full speed(12 Mbps) and low speed(1.5 Mbps).

and I want to operate it at full speed(12 mbps)

--- Quote Start ---

3) Do you have a specific board in mind? Since you mention HSMC, its likely you already have a board.

--- Quote End ---

-->The board I already have is DE2-115 (Cyclone IVE).

http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=139&no=502

--- Quote Start ---

Provide this information and you'll get more help.

Cheers,

Dave

--- Quote End ---

-->Thanks for your response and further infos are available above :)

I reformated your post to remove your answers from the "quote" part, which makes them easier to read. I hope you don't mind ;)

If you go in "resources" on the terasic web page for the AD/DA board, you can download a CD image. This CD probably has some example designs, and even if they don't seem to be made for the DE2-115, you can still see how they interfaced the AD/DAs and reuse some of the code or components in your own design.

Thanks for the suggestion.

I got the pin configuration for ADC available in my board CD of daughter card(AD/DA).

The pin configuration given in that CD even matches with the Pin configuration I generate using "DE2-115 system builder" by selecting clock and HMSC high speed A/D card which I am using currently.

But when I look for pin configuration for HSMC on User Manual of DE2-115, It doesn't match with previous one I mentioned. So, I am a afraid of using it like may be it damage the board.

There is also one Verilog example within the CD of daughter card:

module DE2_115_ADDA(

//////// CLOCK //////////

CLOCK_50,

CLOCK2_50,

CLOCK3_50,

//////// I2C for HSMC //////////

I2C_SCLK,

I2C_SDAT,

//////// HSMC //////////

ADC_CLK_A,

ADC_CLK_B,

ADC_DA,

ADC_DB,

ADC_OEB_A,

ADC_OEB_B,

ADC_OTR_A,

ADC_OTR_B,

DAC_CLK_A,

DAC_CLK_B,

DAC_DA,

DAC_DB,

DAC_MODE,

DAC_WRT_A,

DAC_WRT_B,

OSC_SMA_ADC4,

SMA_DAC4

);

//=======================================================

// PORT declarations

//=======================================================

//////////// CLOCK //////////

input CLOCK_50;

input CLOCK2_50;

input CLOCK3_50;

//////////// I2C for HSMC //////////

output I2C_SCLK;

inout I2C_SDAT;

//////////// HSMC //////////

output ADC_CLK_A;

output ADC_CLK_B;

input [13:0] ADC_DA;

input [13:0] ADC_DB;

output ADC_OEB_A;

output ADC_OEB_B;

input ADC_OTR_A;

input ADC_OTR_B;

output DAC_CLK_A;

output DAC_CLK_B;

output [13:0] DAC_DA;

output [13:0] DAC_DB;

output DAC_MODE;

output DAC_WRT_A;

output DAC_WRT_B;

input OSC_SMA_ADC4;

input SMA_DAC4;

I was not able to add complete code due to following errors: You have included 7 images in your message. You are limited to using 4 images so please go back and correct the problem and then continue again.

As I am going to use only one channel out of 4(ADC_DA) for my purpose(Analog to digital conversion), I will map the 14 bit data pins of FPGA with this one. but I am not sure about which other pins like clock, OTR,OEB, etc will be needed for my purpose.

For first step i am planning to take the signal from AD converter and display corresponding output into red led like this:

library ieee;

use ieee.std_logic_1164.all;

ENTITY part1 IS

PORT ( ADC_DA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);

LEDR : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)

);

END part1;

ARCHITECTURE Behavior OF part1 IS

BEGIN

LEDR <= ADC_DA;

END Behavior;

can anybody make me clear.

--- Quote Start ---

But when I look for pin configuration for HSMC on User Manual of DE2-115, It doesn't match with previous one I mentioned. So, I am a afraid of using it like may be it damage the board.

--- Quote End ---

What are the differences that concern you?

So long as the pin numbers correspond to pins on the connector, the names do not matter.

Look at the schematic of the DE115 and create a table of the net names used in the schematic and the corresponding FPGA pin number. Then add a column for the two different pinouts you have. That will help confirm that the names used in the VHDL examples map to pins that are GPIO.

Successful synthesis with Quartus will also tell you that the pin assignments are valid. However, it will not tell you that the pins you have used actually route to the GPIO header - since that is board specific.

Cheers,

Dave

--- Quote Start ---

There is also one Verilog example within the CD of daughter card:

module DE2_115_ADDA ...

--- Quote End ---

Don't post code inline in messages. It just clutters the forum. There is a "Manage Attachments" button that can be used to add code.

--- Quote Start ---

For first step i am planning to take the signal from AD converter and display corresponding output into red led like this:

--- Quote End ---

Your first step should be to connect the clock and data to the GPIO and use SignalTap to capture a trace of data. SignalTap is an FPGA logic analyzer. Using that interface, you will be able to see what outputs from the DAC do when you control inputs.

Actually, your first step should be to run a Terasic example design. I am sure they must have one. If you cannot find one, contact them and ask for one.

Cheers,

Dave

What is the relation between clock and data rate of digital device(e.g. ADC in my case)??

The ADC of daughter card support up to 65 MSPS(mega sample per second). Does it mean that we can use clock frequency less than 65 MHZ(lets say 50 MHZ or 2 MHZ) but can't use clock frequency greater than 65 MHZ (lets say 100 MHZ) to get output??

I used frequency 100 MHz from its oscillator and didn't get any output.

@dwh@ovro.caltech.edu:: I am using ADA_HSMC instead of GPIO as my daughter card only support HSMC.

Although using HSMC it doesn't make any difference to GPIO while capturing signal with Signal Tap if pin is mapped for HSMC instead of GPIO. Isn't it??