A/D converter-FPGA-USB

What is the relation between clock and data rate of digital device(e.g. ADC in my case)??

The ADC of daughter card support up to 65 MSPS(mega sample per second). Does it mean that we can use clock frequency less than 65 MHZ(lets say 50 MHZ or 2 MHZ) but can't use clock frequency greater than 65 MHZ (lets say 100 MHZ) to get output??

I used frequency 100 MHz from its oscillator and didn't get any output.