about SDC file

Think of it like this, very simplified. It helped me a lot to grasp what was going on.

Using VHDL or whatever you describe some behavior, like a register.

In your RTL simulation rising edge of clock and data would arrive at the register at the exact same time, and the register will hold the data. Real life does not work like that.

What the tool does when synthesizing is to skew or delay the clock a bit, so that data arrives at the register first - then a bit later the rising edge of the clock arrive and the register will work as intended.

The SDC file can be used to describe the clocks in your design - and also set up constraints of your input/output ports etc etc. This helps the synthesizer resolve how it should all be wired together.

M.