About My VHDL Task

huytergen,

You can't do what he asks using the code he sent you. It looks like the reg table is a simple 16 element full sine wave in twos-compliment with an amplitude of 64. You should research DDS (Direct Digital Synthesis) and will find alot of info on the web. The output frequency of a DDS is set by setting a "tuning word" to an appropriate value:

F = M * Fc / 2^n

where F is the sine wave frequency, Fc is the clock frequency, M is the tuning word, and n is the width of the phase accumulator in bits. Normally, the phase accumulator is much wider than the lookup table in order to get the desired frequency resolution. For example, if your clock is 100 Mhz and you want a resolution of 1 Hz, set M to 1 to find 2^n of 10.0e8 so you need n = 27. Most people would just use 32 bit for the phase accumulator and M. Then use the upper 4-bits as an index into your lookup table.

So you will need to change his code to have a phase increment M input into the entity. The way he is incrementing c is very clumsy. It is going from 0 to 15 so it makes much more sense to make it an unsigned 4-bit number that you increment by M in one-line of code. M will also be an unsigned 4-bit number. He has M hardwired to 1, so the output frequency is fixed. In practice, you probably cannot achieve the desires frequencies with a 4-bit phase accumulator and will have to make it much wider.

You can figure out the rest.