Yamada1
Occasional Contributor
Occasional ContributorAbout IO PLL
It would be helpful if you could tell me about the Advanced Parameter tab of the IOPLL Intel FPGA IP settings. PLL is in direct mode. 1) Is it correct to understand that C-Counter-0 Divide Setting i...
Thank you for the device part number. Please refer to the answer below:
- Yes, you are correct. The output clock frequency is the result of the VCO frequency divided by the counter value. Can refer to Figure 64 in below link https://www.intel.com/content/www/us/en/docs/programmable/683461/current/pll-architecture.html
- For this one, I think we used to call it odd division factor, where we use a negative edge clock to normalize the duty cycle to 50/50. Another that, you can take a look on this link https://www.intel.com/content/www/us/en/docs/programmable/683845/current/address-bus-and-data-bus-setting-for-23451.html
- I don't think it affect jitter; it simply uses a falling edge instead of rising edge. If it did affect jitter, we would have to produce a different jitter spec for when that even duty bit is enabled vs disabled.
Regards,
Aqid
