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Honored Contributor

16 years ago

about clock gating for multiple blocks

Hi :

I am now trying to implement clock gating to a large design.

There are 15 basic blocks which works almost in serial sequence. I planed to do the clock gating for them individually.

The global clock is out of a PLL and splitted into 15 clock gating unit and the output of each goes into each blocks.

The problem is these 15 sub-clocks must be synchronized and now there is some timing violation which seems that they are not.

I wonder if there is some constraints to do before synthesis or some smarter way in implenment the clock gating for this design

Thank you very much:) :) :)

11 Replies

Altera_Forum
Honored Contributor
16 years ago
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Yes I see. You should measure in a real hardware setup, if any power saving is achieved with clock gating versus clock enable. If it's still meaningful, all options of clock gating have been discussed. The preferred way is with clock control blocks, otherwise you have to an increased effort to achieve timing closure. If FIFOs would be required for synchronization, the power saving effect is most likely exhausted.
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Yes, I agree with you. :) :)
Anyway, I tried ALTCLKCTRL to use the 'ena' to switch the clk on and off. But the device I am using is Cycloneiii. The usage of ALTCLKCTRL has to be specified as either global or exteranl. If as global, the amount has to be less than 10; if externl, output pins must be assigned. Neither of them is suitable for this design. :confused: :confused: