Honored ContributorWhen using PLL megafunction , I set input clk 15.36MHz ,c1 out 92.16MHz and c2 out 30.72MHz. But after full compilation ,the Timing Analyzer in Compilation report showed the c1 out changed to be 92.17MHz:
Clock Setup: 'PLL1:PLL1_inst|altpll:altpll_component|_clk1' 0.859 ns 92.17 MHz ( period = 10.850 ns ) 100.09 MHz ( period = 9.991 ns ) Does anyone know why? Thanks !
Honored ContributorThis is not strange. PLLs can only produce certain figures. You can tell that before compilation in the megawizard itself(acheived versus required).
However your clocks are divisible by input clk and it is unusual not to get them correctly. What is that 100.09MHz??Honored ContributorCheck the exact PLL integer factors and frequencies in fitter report. As 92.16 is exact integer multiply of the input frequency, it will be surely achieved. 92.17 can be supposed as an incorrect rounded informational value.
P.S.: Strictly spoken, the value 92.17 mhz doesn't mean much without an accuracy information. Unless otherwise noted, +/- 1 least significant digit is a standard accuracy.Honored ContributorThank you for your suggestions!
I have checked it in Fitter report and found the right output frequency 92.16MHz is showed in this report. So, the Timing Analyzer showed a wrong message ?Honored ContributorNot exact, but not completely wrong. As said, there's no specified accuracy for this message.
Honored Contributorbe careful, i believe you can run out of counter/count dividers on those PLL's. You might try turning off "auto merge PLL" options and do a test run using 2 PLL's rather than 1. Good luck.
