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Altera_Forum's avatar
Altera_Forum
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16 years ago

a strange problem about PLL output

When using PLL megafunction , I set input clk 15.36MHz ,c1 out 92.16MHz and c2 out 30.72MHz. But after full compilation ,the Timing Analyzer in Compilation report showed the c1 out changed to be 92.1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

be careful, i believe you can run out of counter/count dividers on those PLL's. You might try turning off "auto merge PLL" options and do a test run using 2 PLL's rather than 1. Good luck.