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Altera_Forum's avatar
Altera_Forum
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16 years ago

a strange problem about PLL output

When using PLL megafunction , I set input clk 15.36MHz ,c1 out 92.16MHz and c2 out 30.72MHz. But after full compilation ,the Timing Analyzer in Compilation report showed the c1 out changed to be 92.1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Check the exact PLL integer factors and frequencies in fitter report. As 92.16 is exact integer multiply of the input frequency, it will be surely achieved. 92.17 can be supposed as an incorrect rounded informational value.

P.S.: Strictly spoken, the value 92.17 mhz doesn't mean much without an accuracy information. Unless otherwise noted, +/- 1 least significant digit is a standard accuracy.