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Altera_Forum's avatar
Altera_Forum
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11 years ago

A Question About Constraints

I understand the clock constraining.

But what about the non-clock signals.

For example, I have a small VHDL design (1 file) that has a several clocks,

a reset, and some LED output signals. The constraint file was generated by

the Terasic people that made the board. When synthesized the results show

the design is NOT constrained. When you look at the constraint file

the reset and LED signals are not in there. When running the Timing Analyzer

it shows the reset and LEDs as unconstrained.

What do you do with them? What constraint, if any do you use? There's very

little literature about this at least I can't find any.

In the past I have usually had them as Set Input Delay constrained to the period

of the clock. Probably has no affect.

Thanks

PWS

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    You can use the following ... basically you cut the timing paths to tell TimeQuest not to analyze them. The cutting of the reset path assumes you have reset synchronizers in your logic (read about reset synchronization in the Quartus handbook). The JTAG paths appear when you use SignalTap II or use the JTAG-to-Avalon-MM bridge. 

    #  -----------------------------------------------------------------#  Clock#  -----------------------------------------------------------------# #  50MHz clock
set clk_period 50MHz
#  External 50MHz clock (internal logic clock)
set clk clkin_50MHz
create_clock -period $clk_period -name $clk 
#  Exclusive clock domain/group
set_clock_groups -exclusive -group 
#  Derive the clock uncertainty parameter
derive_clock_uncertainty
#  -----------------------------------------------------------------#  JTAG#  -----------------------------------------------------------------# 
set ports 
if { == 1} {
   #  JTAG must be in use
   # 
   #  Exclusive clock domain
    set_clock_groups -exclusive -group altera_reserved_tck
   #  Altera JTAG signal names
    set tck altera_reserved_tck
    set tms altera_reserved_tms
    set tdi altera_reserved_tdi
    set tdo altera_reserved_tdo
   #  Cut all JTAG timing paths
    set_false_path -from *                -to 
    set_false_path -from  -to *
    set_false_path -from  -to *
}
#  -----------------------------------------------------------------#  Cut timing paths#  -----------------------------------------------------------------# #  The timing for the I/Os in this design is arbitrary, so cut all#  paths to the I/Os, even the ones that are used in the design,#  i.e., reset and the LEDs.# 
#  External asynchronous reset and push-buttons
set_false_path -from }] -to *
#  LED output path
set_false_path -from * -to }]

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Try to think of it as a design question and not a constraint question. Does XYZ need to occur in a certain amount of time or it won't work. If so, what is that time?

    For LEDs, it shouldn't matter. If it takes 5ns or 50ns to get to them, no one will notice, so leave unconstrained.

    For the reset, it depends. If it's coming in off chip and from an asynchronous source(say a pushbutton), then there is no way to constrain that because the source is not synchronous to the destination. Lots of users synchronize a signal like that(have it feed 2-3 registers) and then have the output of the last register drive your logic. That can be constrained and will be just by the nature of your clock constraints.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thanks to both of you. Very helpful.

    Yes, I have a SignalTap. That thing caused cause 50 or more JTAG signals to appear from nowhere!